1. Field of the Invention
The present invention relates to image processing and more particularly to methods and apparatus for flicker suppression in interlaced video images.
2. Description of the Prior Art
The following are systems representative of the prior art.
"Psuedogaussian Video Output Processing for Digital Display", U.S. Pat. No. 4,215,414, shows a method and apparatus for generating a psuedogaussian characteristic in the display of video information presented in digital form from a read-write memory that is continuously updated as required. Picture elements of each line read for display are summed with a predetermined fraction of the sum of the values of corresponding pixels of adjacent lines above and below the current line thus forming a vertical psuedogaussian calculation for the pixels of the current line. Horizontal psuedogaussian calculation of the pixels is then performed in a similar manner using two pixel delay elements connected in cascade and connected to an adder to sum values of pixels p-1 and p+1 as an input to a second adder which sums the output of the first adder divided by a predetermined value with the value of pixel p.
The flicker suppression method of the patent employs linear convolution techniques to provide an approximation of the gaussian characteristics of the signal source.
The patent does not teach a method of flicker suppression in accordance with the present invention where pixel intensity values are tested against a first threshold and then intensity values of adjacent pixels are may be modified or flagged to reduce the perception of flicker.
The prior art discussed above does not teach nor suggest the present invention as disclosed and claimed herein.